The company is seeking a Physical Verification Engineer for a 12-month contract with a salary of 6,500. The role involves developing and maintaining DRC, LVS, ANT, ERC, ESD, and PERC rule decks, as well as performing full-chip physical verification sign-off and collaborating with design, manufacturing, and IP teams to resolve layout and DRC issues. Candidates should possess a Bachelor’s or Master’s degree in Electrical or Electronics Engineering. The position requires technical expertise in physical verification processes and automation solutions to enhance tape-out flow efficiency.
This summary is AI-generated and may contain inaccuracies. Please refer to the full job description below.
[This job id 21174 first appeared in Job-Q.com on 23 Jul 2026]
Job responsibilities
Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes.
Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
Co-work with Place & Route team to resolve full-chip layout integration issues.
Coordinates with internal IP owners on IP related issues.
Coordinates with Manufacturing Team on DRC related issues.
Provide automation solutions to improve efficiency in tape-out flow.
Report on tapeout PV issues.
Job requirements:
Bachelor/Master’s Degree in Electrical/Electronic Engineering/Computer Science
Familiar with IC Design front-to-backend flow
Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
Proficient in script programming, such as Python, TCL, Perl, or C-shell
Proficient in UNIX (Linux) platforms
Strong communication skills, problem solving and analytical skills.
Interested candidates may send resumes to khaiven.tay@persolapac.com or apply through the application system. Regret to inform that only shortlisted candidates will be notified.
PERSOL Singapore Pte Ltd • RCB No. 200007268E
EA License No. 01C4394 • EA Registration No. R21101254 (Tay Khai Ven)
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