Editorial summary

The company is seeking a Senior/IC Design Engineer specializing in Design Verification to develop and execute verification plans for Pre-Silicon IP, ASIC, and SoC designs. The role involves building SystemVerilog/UVM-based verification environments, developing directed and constrained-random tests, and analyzing simulation results to ensure design correctness. Key requirements include experience with verification methodologies, debugging skills, and collaboration across teams. The position offers a salary of 10,000.

This summary is AI-generated and may contain inaccuracies. Please refer to the full job description below.

Job description

[This job id 17585 first appeared in Job-Q.com on 01 Jul 2026]

Job Description

  • Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
  • Build and maintain SystemVerilog/ UVM-based verification environments and testbenches
  • Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
  • Debug DUT issues, analyze simulation results, and drive verification closure.
  • Collaborate with cross-functional teams throughout the design and verification lifecycle.
  • Support regression automation and continuously improve verification methodologies.
  • Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.

Requirements

  • Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience.
  • Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
  • Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
  • Experience with industry-standard EDA tools (e.g., Cadence or Synopsys).
  • Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
  • Strong analytical, problem-solving, and communication skills.

We invite qualified candidates to apply online or submit a detailed resume to resume@aurexis-tech.com

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Job Summary

  • Published on: 01 Jul, 2026
  • Category: Engineering
  • Vacancy: 1
  • Job type: Full Time
  • Salary: 10000
  • Location: On site
  • Job Nature: Full Time

Company Details