Editorial summary

The company is seeking a Senior IC Layout Engineer to join their semiconductor team in Ang Mo Kio. The role involves developing and implementing layout designs, including floor planning, device placement, and signal routing, while ensuring compliance with industry standards through various physical verification processes. The position offers a basic salary of $7,500 along with meal allowances, variable bonuses, and medical benefits, on a permanent, five-day workweek basis. Candidates are expected to have experience in IC layout design and relevant physical verification procedures.

This summary is AI-generated and may contain inaccuracies. Please refer to the full job description below.

Job description

[This job id 30845 first appeared in Job-Q.com on 09 Sep 2026]

Job Description

• Industry/ Organization Type: Semiconductor
• Position Title: Senior IC Layout Engineer
• Working Location: Ang Mo Kio
• Working Hours: 5 Days (Monday – Friday, 9:00 AM – 6:00 PM)
• Salary Package: Basic Salary + Meal Allowance + VB + Medical & Dental Benefits
• Duration: Permanent Role

Key Responsibilities

• Develop layout designs based on schematic presentations.
• Implement layout designs, including the following:
• Floor planning and device placement.
• Power and signal routing, including signal and power integrity optimization.
• Perform DRC/LVS/ERC/ANT/ESD/PERC/LVL and other required physical verification checks.
• Ensure designs pass DRC requirements and meet LVS requirements.
• Prepare layout materials and conduct layout reviews.
• Follow checklists and methodologies to ensure layout quality.
• Improve and enhance layout methodologies.
• Participate in post-layout adjustments and block/IP-related activities.
• Apply a good understanding of AMS layout fundamentals, EMIR, RC delay, decoupling capacitors, and latch-up.
• Mentor and provide guidance to less experienced layout engineers.
• Participate in developing layout best practices and methodologies.
• Other ad-hoc duties as assigned.

APPLY NOW!!!

• Diploma or Bachelor's Degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or an equivalent qualification.
• At least 6 years of hands-on experience in layout engineering.
• Experience with technology nodes below 16nm, high-speed or RF layout, and leading CAD tools, methodologies, and FinFET technology.
• Experience with Cadence SKILL or equivalent tools for PCell development, including Perl, Python, or TCL, and automation to improve layout productivity.
• Good understanding of process technology, circuit design, and CAD setup for analog layout physical verification.
• Experience with TX/RX/PLL/ADC/DAC and analog/digital chip-top integration is an advantage.
• Experience providing layout guidance to team members and ensuring layout quality.

Kindly apply through ANY of the following methods:

• Submit your application by clicking the APPLY button;
• Email your resume to . Please indicate #10248 on the email subject.

Anradus Application Policy: We value each application and ensure every resume is reviewed. Our process is efficient, typically concluding within 3 working days. If you do not receive communication from us within this timeframe, it's likely that your application has not been shortlisted by our client. In such cases, we recommend continuing your job search to maximize your opportunities.

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