Editorial summary

The company is seeking a Senior/IC Design Engineer specializing in Physical Design to perform RTL-to-GDS physical implementation of ASIC IP, subsystems, and SoCs using advanced EDA tools and AI-assisted methodologies. The role involves developing and executing synthesis, DFT, and timing closure strategies, including DRC/LVS, STA, and GDS tape-out verification, while collaborating with cross-functional teams to meet PPA and timing objectives. Candidates should have expertise in synthesis, DFT, STA scripting, and industry-standard design verification processes. The position offers a salary of 10,000.

This summary is AI-generated and may contain inaccuracies. Please refer to the full job description below.

Job description

[This job https://singapore.job-q.com/jobs/detail/senior-ic-design-engineer-physical-design-33892 first appeared in Job-Q.com on 22 Sep 2026]

Job Description

• Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoCdesigns using industry-leading EDA tools and AI-assisted methodologies,
• Develop and execute synthesis, Design-for-Test (DFT), and timing closure strategies, including DRC/LVS, static timing analysis (STA), scan/DFT validation, and GDS tape-out verification, leveraging AI-assisted methodologies to achieve successful tape-out.
• Collaborate with cross-functional stakeholders to achievepower, performance, area (PPA), and timing goals.
• Design, implement, and maintain synthesis, DFT, and STAscripts using industry best practices to improve automation, flow robustness,and design quality.
• Leverage AI/LLM tools to automate workflows, accelerateanalysis, optimize place-and-route (PnR) and timing prediction, and generatedesign constraints to improve productivity and design quality.

Requirements

• Bachelor/Master Degree in Electronics/Electrical/Computer Engineering, or a related field, with at least 1 year of relevant experience.
• Experience in RTL-to-GDS physical design, including synthesis, floorplanning, placement, Layout, clock tree synthesis (CTS),routing, timing closure, physical verification, and design optimization.
• Good understanding of timing constraints development and Static Timing Analysis (STA).
• Demonstrated use of LLMs and AI coding assistants to automate workflows, debug scripts, and generate documentation.
• Proficiency in scripting (Tcl, Python, Perl, Shell, andMakefile), as well as Verilog, SystemVerilog, C, and C++.
• Experience with AI-assisted backend EDA tools (e.g.,Synopsys, Cadence) is preferred.
• Self-motivated team player with strong verbal and written communication skills.

We invite qualified candidates to submit your CV to or apply online.

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